Alright, in order to hopefully prompt some actual discussion about Nanotechnology, let me bring a few links to your attention.
First, H+ has a new article on Molecular Assembly: http://hplusmagazine...-nanostructures
Recently, a team led by Dr. Ting Xu at the U.S. Department of Energy's Lawrence Berkeley National Laboratory made an important advance towards this nanotechnology goal. They found a simple and yet powerful way to induce nanoparticles to assemble themselves into complex arrays. By adding specific types of small molecules to mixtures of nanoparticles and polymers, Dr. Xu's group directed the self-assembly of the nanoparticles into arrays of one, two and three dimensions with no chemical modification of either the nanoparticles or the block copolymers. In addition, they found that the application of external stimuli – light and/or heat – can be used to further direct the assemblies of nanoparticles for even finer and more complex structural details.
Next, Next Big Future also made an interesting post: http://nextbigfuture...-in-carbon.html
“While batteries have large storage capacity, they take a long time to charge; while electrostatic capacitors can charge quickly but typically have limited capacity. However, supercapacitors/electrochemical capacitors incorporate the advantages of both,” Bandaru said.
Defects on nanotubes create additional charge sites enhancing the stored charge. The researchers have also discovered methods which could increase or decrease the charge associated with the defects by bombarding the CNTs with argon or hydrogen.
Carbon nanotubes could serve as supercapacitor electrodes with enhanced charge and energy storage capacity.
Additionally, a first generation CN semi-conductor usable in flexible OLED displays: http://nextbigfuture...usable-for.html
The USC researchers make large arrays of carbon nanotube transistors using solution-processing techniques at room temperature. They start by placing a silicon wafer in a chemical bath to coat its surface with a nanotube-attracting chemical, then rinse off the residue. The treated wafer is then immersed in a solution of semiconducting carbon nanotubes, which are attracted to its surface. The wafer, now coated with a carpet of nanotubes, is rinsed clean again. To make transistors from this tangled mess, the researchers put down metal electrodes at selected locations. The electrodes define where each transistor is and carry electrons into and out of the nanotubes that lie between them. Areas of silicon underlying each device act as the transistors' gates. So far, they've built a prototype device on a four-inch silicon wafer and used it to control a simple organic light-emitting diode display.
The USC researchers are working to build a truly integrated organic LED display that is flexible and transparent.
On top of this, we now can make precise circuit arrays of nanotubes by using a DNA scaffold to position CNs: http://nextbigfuture...tubes-into.html
A central challenge in nanotechnology is the parallel fabrication of complex geometries for nanodevices. Here we report a general method for arranging single-walled carbon nanotubes in two dimensions using DNA origami—a technique in which a long single strand of DNA is folded into a predetermined shape. We synthesize rectangular origami templates (75 nm 95 nm) that display two lines of single-stranded DNA 'hooks' in a cross pattern with 6 nm resolution. The perpendicular lines of hooks serve as sequence-specific binding sites for two types of nanotubes, each functionalized non-covalently with a distinct DNA linker molecule. The hook-binding domain of each linker is protected to ensure efficient hybridization. When origami templates and DNA-functionalized nanotubes are mixed, strand displacement-mediated deprotection and binding aligns the nanotubes into cross-junctions. Of several cross-junctions synthesized by this method, one demonstrated stable field-effect transistor-like behaviour. In such organizations of electronic components, DNA origami serves as a programmable nanobreadboard; thus, DNA origami may allow the rapid prototyping of complex nanotube-based structures.
Now add in reliable manufacturing of graphene in a manner similar to the creation of silicon circuits: http://www.nanowerk....ewsid=13456.php
Inspired by previous work in which scientists grew graphene on copper foil, the team grew the graphene directly onto silicon wafers coated with a special evaporated copper film. They then cut the graphene films into their desired shapes using such standard methods as photolithography, and removed the underlying copper with a chemical solution. What was left was a graphene film that draped down over the silicon wafer with little defect.
And of course the fact that the shuttle just tested a CN based RAM module on the shuttle...
So... what does all this mean?
In my opinion, I think it means we'll have a robust nanotube based computer within five years. A sort of in between hybrid of current silicon technology and a full CN based nanocomputer.
So, what are your opinions?